Non-destructive inverse modeling of copper interconnect structure for 90nm technology node

• Published in: International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003 pp. 31 - 34
• Main Authors: Kunikiyo, T., Watanabe, T., Kanamoto, T., Asazato, H., Shirota, M., Eikyu, K., Ajioka, Y., Makino, H., Ishikawa, K., Iwade, S., Inoue, Y., Yamashita, K., Kobayashi, M., Gohda, A., Oda, Y., Yamaguchi, R., Umimoto, H., Ohtani, K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• Subjects: Capacitance measurement; Copper; Current measurement; Dielectric measurements; Feedback; Inverse problems; Parameter extraction; Parasitic capacitance; Process control; Testing
• ISBN: 0780378261; 9780780378261
• DOI: 10.1109/SISPAD.2003.1233630

We propose non-destructive inverse modeling of copper interconnect cross-sectional structures, which reproduces the pitch dependence of intraand interlayer coupling capacitance parasitic to the interconnect. The coupling capacitances, as well as fringing capacitance, are measured by a proposed test structure based on the charge-based capacitance measurement (CBCM) method (J. C. Chen et al., Tech. Dig. of IEDM, p.69-72, 1996). The present methodology not only provides accurate assessment of actual capacitance variation but provides valuable feedback on the variability of physical parameters such as interlayer dielectric (ILD) thickness and interconnect drawn width reduction or swelling for process control as well. It also ensures the accuracy of LPE (layout parameters extraction) for the 90 nm technology node and beyond.