A comparison of Phase Locked Loop and FIFO Locked Loop

A comparison of Phase Locked Loop and FIFO Locked Loop

In this paper we present a comparison of two methods to control the reading frequency of a First In First Out (FIFO) memory. The first method is based on the monitoring of its filling level and the other uses the synthesis of the writing frequency to generate and control the reading frequency. These...

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Bibliographic Details
Published in:2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 1314 - 1317
Main Authors: Bassan, Fabio R., Akira Nakandakare, Cleber, de Barros, Luis Paulo F., Rocha Pereira, Fernando, Salvador, Arley
Format: Conference Proceeding
Language:English
Published: IEEE 01-08-2013
Subjects:
Clocks
Frequency control
Frequency synthesizers
Phase locked loops
Protocols
Writing
Online Access:Get full text
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Summary:In this paper we present a comparison of two methods to control the reading frequency of a First In First Out (FIFO) memory. The first method is based on the monitoring of its filling level and the other uses the synthesis of the writing frequency to generate and control the reading frequency. These control systems are used in data communication protocol justification architecture for tributary signal demapping.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2013.6674897