Placement and Routing by Overlapping and Merging QCA Gates

• Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 5
• Main Authors: Fontes, Geraldo, Silva, Pedro Arthur R. L., Nacif, Jose Augusto M., Vilela Neto, Omar P., Ferreira, Ricardo
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2018
• Subjects: Adders; Clocks; Layout; Logic gates; Partitioning algorithms; Routing; Wires
• ISSN: 2379-447X
• DOI: 10.1109/ISCAS.2018.8351001

The QCA gate-level design introduces new challenges to the traditional mapping, placement, and routing flow. First, the wires consume more than 90% of total area. In addition, even a combinational circuit requires a clock scheme, and all internal paths should be balanced. This work proposes a novel approach to automatically map a gate-level circuit onto a QCA layout by using a merge overlapping approach, and a universal clock scheme to provide scalability. First, the circuit is decomposed into a set of overlapping subgraph partitions. This decomposition is guided by reconvergent paths. For each subgraph, more than one customized QCA layout cell is generated on-the-fly. During the last step, a merge overlapping algorithm rebuilds the entire circuit to produce the final layout. All inter and intra-partition wires should be balanced according to the adopted clock scheme. Our approach reduces the total area in more than 50% in comparison to a previous approach based on standard-cell QCA libraries. Finally, all layouts were validated on QCA Designer simulator to verify the design rules.