Metrology and inspection for process control during bonding and thinning of stacked wafers for manufacturing 3D SIC's

• Published in: 2011 IEEE 61st Electronic Components and Technology Conference (ECTC) pp. 999 - 1002
• Main Authors: Halder, S., Jourdain, A., Claes, M., de Wolf, I., Travaly, Y., Beyne, E., Swinnen, B., Pepper, V., Guittet, P-Y, Savage, G., Markwort, L.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2011
• Subjects: Integrated optics; Metrology; Optical interferometry; Optical reflection; Optical scattering; Three dimensional displays; Through-silicon vias
• ISBN: 1612844979; 9781612844978
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2011.5898631

New challenges for wafer metrology solutions have evolved with 3D-IC manufacturing technology. 3D-IC technology allows stacking single chips, electrically connecting them in the vertical direction, and then forming a chip structure with significant advantages over traditional chips. However, before the 3D-stacking of IC's becomes a mainstream process numerous metrology issues need to be solved. In this paper we discuss the critical in-line metrology needs during bonding and thinning of the device wafers before stacking. We show how TSV depth variations, glue layer defects and grinding issues require monitoring for a successful 3D integration.