A test system for characterization of ASIC and CdTe hybrid pixel detectors

• Published in: 2011 IEEE Nuclear Science Symposium Conference Record pp. 845 - 850
• Main Authors: Mohan, A., Panjkovic, G., Fitrio, D., Veljanovski, R., Farmer, C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-10-2011
• Subjects: Data acquisition; Electronic mail; Field programmable gate arrays; Generators
• ISBN: 1467301183; 9781467301183
• ISSN: 1082-3654; 2577-0829
• DOI: 10.1109/NSSMIC.2011.6154552

An in-house analogue Application Specific Integrated Circuit (ASIC) which is used as readout electronics in a hybrid pixel detector (HPD) has been developed. The ASIC and HPD (ASIC and CdTe bump bonded), are part of a program aimed at developing a high performance HPD module for imaging applications with high photon rates. This paper describes a custom designed and built test bench system that has been developed in order to evaluate both the ASIC and HPD performance thoroughly. The major modules of the system are: National Instruments (NI) Flex-RIO data acquisition system, evaluation PCB (a PCB that holds an ASIC or HPD during electrical and radiation testing), Arbitrary Wave Generator (AWG) and High Voltage (HV) power supply. The development of a new vertical scanning table and software drivers is in the progress, which will be an integral part of the test bench. It will be used to substitute the currently used mechanical platform, in order to improve: load, accuracy and speed capabilities.