Improved fault emulation for synchronous sequential circuits

• Published in: 8th Euromicro Conference on Digital System Design (DSD'05) pp. 72 - 78
• Main Authors: Raik, J., Ellervee, P., Tihhomirov, V., Ubar, R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Costs; Emulation; Field programmable gate arrays; Hardware; Sequential circuits; Test pattern generators
• ISBN: 0769524338; 9780769524337
• DOI: 10.1109/DSD.2005.50

Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated to fault emulation for sequential circuits are explained and alternative implementations are discussed. An environment for hardware emulation of fault simulation is presented. It incorporates hardware support for fault dropping. The proposed approach allows simulation speed-up of 40 to 500 times as compared to the state-of-the-art in fault simulation. Average speedup provided by the method is 250 that is about an order of magnitude higher than previously cited in the literature. Based on the experiments, we can conclude that it is beneficial to use emulation when large numbers of test vectors is required.