Impact of BEOL, multi-fingered layout design, and gate protection diode on intrinsic MOSFET threshold voltage mismatch

Impact of BEOL, multi-fingered layout design, and gate protection diode on intrinsic MOSFET threshold voltage mismatch

Continued scaling down of MOSFETs, compounded with limitation in process variation control capabilities, has made MOSFET mismatch more significant for advanced technologies. In order to prevent over compensating for MOSFET mismatch in design margin, it is important to characterize the intrinsic MOSF...

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Bibliographic Details
Published in:2007 IEEE Conference on Electron Devices and Solid-State Circuits pp. 1059 - 1062
Main Authors: Lim, G.H., Zhou, X., Khu, K., Yoo, Y.K., Poh, F., See, G.H., Zhu, Z.M., Wei, C.Q., Lin, S.H., Zhu, G.J.
Format: Conference Proceeding
Language:English
Published: IEEE 01-12-2007
Subjects:
Diodes
Monitoring
MOSFET circuits
Probes
Process control
Protection
Routing
Testing
Threshold voltage
Tiles
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Summary:Continued scaling down of MOSFETs, compounded with limitation in process variation control capabilities, has made MOSFET mismatch more significant for advanced technologies. In order to prevent over compensating for MOSFET mismatch in design margin, it is important to characterize the intrinsic MOSFET mismatch accurately. In this paper, test structures are designed to study the influence of back end of line (BEOL), multi-fingered layout, and gate protection diode (GPD) on MOSFET threshold voltage mismatch characterization.
ISBN:9781424406364
1424406366
DOI:10.1109/EDSSC.2007.4450310