High-performance Substrate Design for DRAM Flip-chip Interconnection using Etch-back Process

• Published in: 2007 Proceedings 57th Electronic Components and Technology Conference pp. 323 - 328
• Main Authors: Jongjoo Lee, Sungho Mun, Soonyong Hur, Tae-Gyeong Chung, Younghee Song
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2007
• Subjects: Bonding; Costs; Delay; Design methodology; Etching; Graphics; Load flow; Packaging; Random access memory; Tin
• ISBN: 9781424409846; 1424409845
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2007.373817

To apply an Au-stud bumping, which has the merit of being a supportable fine pad/bump pitch comparable to that of conventional wire-bonding, in the high-reliable, low-cost flip-chip packaging of high-speed DRAMs with a central dual-inline chip pad configuration, a new design method of the flip-chip package substrate was developed. In the method, a narrow, through-center plating line was formed between dual-in-line bump pads, all of which were connected to the central plating line. After thick electroplating of the bump pads for the reliable joint formation between an Au-stud bump and a package substrate, the central plating line was etched out. The Au-stud flip-chip substrate design method was applied to a 512 Mb GDDR4 DRAM, together with the PCB interconnect design to obtain balanced parasitics and improved power delivery, and the resulting 2-layer flip-chip package, showed improved performance, especially, at low supply voltage over the conventional 2-layer BOC package for the device.