6T SRAM design for wide voltage range in 28nm FDSOI

• Published in: 2012 IEEE International SOI Conference (SOI) pp. 1 - 2
• Main Authors: Thomas, O., Zimmer, B., Pelloux-Prayer, B., Planes, N., Akyel, K.-C, Ciampolini, L., Flatresse, P., Nikolic, B.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-10-2012
• Subjects: Bit error rate; Clocks; High definition video; Leakage current; MOSFETs; Random access memory
• ISBN: 9781467326902; 1467326909
• ISSN: 1078-621X; 2577-2295
• DOI: 10.1109/SOI.2012.6404393

Unique features of the 28nm ultra-thin body and buried oxide (UTBB) FDSOI technology enable the operation of SRAM in a wide voltage range. Minimum operating voltage limitations of a high-density (HD) 6-transistor (6T) SRAM can be overcome by using a single p-well (SPW) bitcell design in FDSOI. Transient simulations of dynamic failure metrics suggest that a HD 6T SPW array with 128 cells per bitline operates down to 0.65V in typical conditions with no assist techniques. In addition, a wide back-bias voltage range enables run-time tradeoffs between the low leakage current in the sleep mode and the short access time in the active mode, making it attractive for high-performance portable applications.