Incorporating Energy and Throughput Awareness in Design Space Exploration and Run-Time Mapping for Heterogeneous MPSoCs

• Published in: 2013 Euromicro Conference on Digital System Design pp. 513 - 521
• Main Authors: Pham, Nam Khanh, Singh, Amit Kumar, Kumar, Akash, Aung, Khin Mi Mi
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2013
• Subjects: design space exploration; Energy consumption; Hardware; heterogeneous MPSoC; mapping algorithm; Measurement; Optimization; Throughput; Tiles
• DOI: 10.1109/DSD.2013.61

The advancement in process technology has enabled integration of different types of processing cores into a single chip towards creating heterogeneous Multiprocessor Systems-on-Chip (MPSoCs). While providing high level of computation power to support complex applications, these modern systems also introduce novel challenges for system designers, like managing a huge number of mappings (application tasks to processing cores allocations) that increases exponentially with the number of cores and their types. This paper presents a mapping approach that computes multiple energy-throughput trade-off points (mappings) at design-time and uses one of these points at run-time based on desired throughput and current resource availability while optimizing for the overall energy consumption. While significantly reducing the complexity of the design space exploration (DSE) to compute mappings at design-time, the proposed strategy still evaluates mappings for all the resource combinations of the platform, providing efficient mapping solutions for all the scenarios of system architecture at run-time. Moreover, the proposed approach performs energy-aware mapping at run-time while utilizing the DSE results. Experimental results show that proposed strategy achieves better energy-throughput trade-off points, covers all the resource combinations and reduces energy consumption up to 24.93% at design-time and additionally 17.8% at run-time when compared to state-of-the-art techniques.