Optimization of Reliability of Copper Column Flip Chip Packages with Variable Compliance Interconnects

• Published in: 2007 9th Electronics Packaging Technology Conference pp. 499 - 503
• Main Authors: Tay, A.A.O., Siow Ling Ho
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-12-2007
• Subjects: Copper; Electronics packaging; Fatigue; Finite element methods; Flip chip; Integrated circuit interconnections; Integrated circuit packaging; Parametric study; Soldering; Wafer scale integration
• ISBN: 9781424413249; 1424413249
• DOI: 10.1109/EPTC.2007.4469820

This paper describes a parametric study of the reliability of solder joints in wafer level flip chip packages that employ copper column interconnects. In this study, the impact of the change in the compliance of the copper column interconnects on the fatigue life of the solder joints were investigated by varying the diameter of the copper column interconnects. 2-D elastic-plastic finite element analyses were carried out on packages with constant interconnect diameter as well as those with variable interconnect diameters within the same package. The effect of changing the pitch and the pad size were also studied. It was found that an effective strategy in increasing the fatigue life and hence the reliability of the solder joints is by distributing copper columns of lower compliance (greater diameter) near the center of the package and increasing the compliance of the copper columns (decreasing their diameter) towards the perimeter of the chip package. In addition, elastic- plastic-creep analysis was also performed on the packages. It was observed that the results from the elastic-plastic analysis and the elastic-plastic-creep analysis exhibit the same trend.