Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling

As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. We describe an alternative approach, which we call a multiple clock domain (MCD) processor, in which the chip is d...

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Bibliographic Details

Published in:	Proceedings Eighth International Symposium on High Performance Computer Architecture pp. 29 - 40
Main Authors:	Semeraro, G., Magklis, G., Balasubramonian, R., Albonesi, D.H., Dwarkadas, S., Scott, M.L.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 2002
Subjects:	Clocks Costs Delay Dynamic voltage scaling Energy efficiency Frequency conversion Frequency synchronization Potential energy Process design Wire
Online Access:	Get full text
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