50 nm Vertical Replacement-Gate (VRG) pMOSFETs

• Published in: International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138) pp. 65 - 68
• Main Authors: Sang-Hyun Oh, Hergenrother, J.M., Nigam, T., Monroe, D., Klemens, F.P., Kornblit, A., Mansfield, W.M., Baker, M.R., Barr, D.L., Baumann, F.H., Bolan, K.J., Boone, T., Ciampa, N.A., Cirelli, R.A., Eaglesham, D.J., Ferry, E.J., Fiory, A.T., Frackoviak, J., Garno, J.P., Gossmann, H.J., Grazul, J.L., Green, M.L., Hillenius, S.J., Johnson, R.W., Keller, R.C., King, C.A., Kleiman, R.N., Lee, J.T.-C., Miner, J.F., Morris, M.D., Rafferty, C.S., Rosamilia, J.M., Short, K., Sorsch, T.W., Timko, A.G., Weber, G.R., Wilk, G.D., Plummer, J.D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2000
• Subjects: Doping; Etching; Fabrication; Ion implantation; MOSFETs; Rapid thermal processing; Reluctance generators; Surface contamination; Thermal engineering; Ultra large scale integration
• ISBN: 9780780364387; 0780364384
• DOI: 10.1109/IEDM.2000.904260

We present the first p-channel Vertical Replacement-Gate (VRG) MOSFETs. Like the VRG-nMOSFETs demonstrated last year, these devices show promise as a successor to planar MOSFETs for highly-scaled ULSI. Our pMOSFETs retain the key features of the nMOSFETs and add channel doping by ion implantation and raised source/drain extensions (SDEs). We have significantly improved the core VRG process to provide high-performance devices with gate lengths of 100 nm and below. Since both sides of the device pillar drive in parallel, the drive current per /spl mu/m of coded width can far exceed that of planar MOSFETs. Our 100 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ drive 615 /spl mu/A//spl mu/m at 1.5 V with I/sub OFF/=8 nA//spl mu/m-80% more drive than specified in the 1999 ITRS Roadmap at the same I/sub OFF/. We demonstrate 50 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ that approach the 1.0 V roadmap target of I/sub ON/=350 /spl mu/A//spl mu/m at I/sub OFF/=20 nA//spl mu/m without the need for a hyperthin (<20 /spl Aring/) gate oxide.