Parametric study of a VLSI plastic package using locally refined finite element models

• Published in: Fifth Annual IEEE Semiconductor Thermal and Temperature Measurement Symposium pp. 52 - 58
• Main Authors: Simon, B.R., Yuan, Y., Umaretiya, J.R., Prince, J.L., Staszak, Z.J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1989
• Subjects: Adhesives; Bonding; Electronics packaging; Encapsulation; Fabrication; Finite element methods; Parametric study; Plastic packaging; Thermal stresses; Very large scale integration
• DOI: 10.1109/STHERM.1989.76066

The authors present a parametric study of thermal stresses in plastic packages that are induced during the die attachment and encapsulation fabrication steps. Finite-element models (FEMs) of plastic VLSI packages were used to vary package design parameters (die thickness, die bond materials and thickness, lead frame thickness, and package thickness and width/length) over typical ranges. Areas of complexity were considered in more detail using local finite-element analysis. The loss of adhesion between the mold and the die and/or lead frame in the package was simulated using gap finite elements in order to consider the extreme cases of no slip or no adhesion at these material interfaces. Changes in die thickness, die bond thickness, and package thickness caused significant changes in package thermal stresses, whereas changes in lead frame thickness, package width/length and die bond elastic modulus corresponded to minor changes in package stresses. The loss of adhesion at the mold material interface resulted in significantly altered thermal stress fields, e.g. the stresses were concentrated near the corners of the chip and lead frame where cracking has been observed in DIP plastic molding materials.< >