Improvement of thermal stability of via resistance in dual damascene copper interconnection

• Published in: International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138) pp. 123 - 126
• Main Authors: Oshima, T., Tamaru, T., Ohmori, K., Aoki, H., Ashihara, H., Saito, T., Yamaguchi, H., Miyauchi, M., Torii, K., Murata, J., Satoh, A., Miyazaki, H., Hinode, K.
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 2000
• Subjects: Adhesives; Annealing; Circuit stability; Cooling; Copper; Integrated circuit interconnections; Thermal degradation; Thermal resistance; Thermal stability; Tin
• ISBN: 9780780364387; 0780364384
• DOI: 10.1109/IEDM.2000.904273

Thermal stability of via resistance in the multilevel dual damascene Cu interconnection was investigated. The via resistance stability strongly depends on via size, via density and width of connecting Cu wires. The significant via-resistance shift was introduced by stress-induced voiding. To avoid the voiding failure, optimization of heat treatments after electroplating (EP)-Cu deposition are necessary for both stability of Cu films and adhesion of barrier layer with Cu. Thermal stress balance between Cu wires and inter-level-dielectric (ILD) is also important to suppress the via degradation. The dual damascene structure with lower-stress and lower-Young's modulus ILD films such as FSG can provide wider process windows for the stability of the via resistance.