Process development of multi-die stacking using 20 um pitch micro bumps on large scale dies

• Published in: 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC) pp. 318 - 321
• Main Authors: Lee Jong Bum, Li, Jerry Aw Jie, Woo, Daniel Rhee Min
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-12-2014
• Subjects: Bonding; Etching; Filling; Metallization; Stacking; Three-dimensional displays; Through-silicon vias
• DOI: 10.1109/EPTC.2014.7028303

In the 3D integration, multiple chip stacking structure requires large numbers of interconnections inside of each chip. 3D integration, however, encounters several fundamental technology challenges which are Cu TSV expansion, transistor degradation or open failures on Cu contamination, micro-bump stress, and so on. The reliability issues on TSV and micro-bumps are very critical at the stacked chip package as well as during the wafer level processes. Micro-bumps used in this study have 10 μm diameters on TSVs and are placed with 20 μm pitch. The diameter of TSV which used in the study is 5μm. Total 122,054 bumps on each chip which was thinned down to 50 μm are fabricated and stacked for 6 die stacking. Measured electrical resistance was well matched with calculated electrical resistance.