A New Metal Control Gate Last process (MCGL process) for high performance DC-SF (Dual Control gate with Surrounding Floating gate) 3D NAND flash memory

• Published in: 2012 Symposium on VLSI Technology (VLSIT) pp. 19 - 20
• Main Authors: Yoohyun Noh, Youngsoo Ahn, Hyunseung Yoo, Byeongil Han, Sungjae Chung, Keonsoo Shim, Keunwoo Lee, Sanghyon Kwak, Sungchul Shin, Iksoo Choi, Sanghyuk Nam, Gyuseog Cho, Dongsun Sheen, Seungho Pyi, Jongmoo Choi, Sungkye Park, Jinwoong Kim, Seokkiu Lee, Aritome, S., Sungjoo Hong, Sungwook Park
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 01-06-2012
• Subjects: Flash memory; Logic gates; Metals; Process control; Resistance; Shape; Very large scale integration
• ISBN: 9781467308465; 1467308463
• ISSN: 0743-1562
• DOI: 10.1109/VLSIT.2012.6242440

A new Metal Control Gate Last process (MCGL process) has been successfully developed for the DC-SF (Dual Control gate with Surrounding Floating gate cell)[1] three-dimensional (3D) NAND flash memory. The MCGL process can realize a low resistive tungsten (W) metal word-line with high-k IPD, a low damage on tunnel oxide/IPD, and a preferable FG shape. And also, a conventional bulk erase can be used, replaced GIDL erase in BiCS[3][4], due to direct connection between channel poly and p-well by the channel contact holes. Therefore, by using MCGL process, high performance and high reliability of DC-SF cell can be achieved for MLC/TLC 256Gb/512Gb 3D NAND flash memories.