High performance Hybrid and Monolithic Backside Thinned CMOS Imagers realized using a new integration process

High performance Hybrid and Monolithic Backside Thinned CMOS Imagers realized using a new integration process

Hybrid and monolithic thinned backside illuminated CMOS imagers operating at full depletion at low substrate voltages were developed. The combination of a 50 mum EPI layer with varying doping concentration and trenches to reduce crosstalk is unique. All thin wafer processing is performed on 200 mm w...

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Bibliographic Details
Published in:2006 International Electron Devices Meeting pp. 1 - 4
Main Authors: De Munck, K., Sabuncuoglu Tezcan, D., Borgers, T., Ruythooren, W., De Moor, P., Sedky, S., Toccafondi, C., Bogaerts, J., Van Hoof, C.
Format: Conference Proceeding
Language:English
Japanese
Published: IEEE 01-12-2006
Subjects:
CMOS image sensors
CMOS process
Crosstalk
Dark current
Detectors
Doping
Glass
Low voltage
Pixel
Sensor arrays
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Summary:Hybrid and monolithic thinned backside illuminated CMOS imagers operating at full depletion at low substrate voltages were developed. The combination of a 50 mum EPI layer with varying doping concentration and trenches to reduce crosstalk is unique. All thin wafer processing is performed on 200 mm wafers using a specially developed temporary carrier process. As a result, working imagers exhibiting high pixel yield, high quantum efficiency and low dark current are demonstrated
ISBN:142440438X
9781424404384
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2006.346979