Tri-gate bulk CMOS technology for improved SRAM scalability

• Published in: 2010 Proceedings of the European Solid State Device Research Conference pp. 142 - 145
• Main Authors: Changhwan Shin, Nikolić, Borivoje, Tsu-Jae King Liu, Chen Hua Tsai, Mei Hsuan Wu, Chung Fu Chang, You Ren Liu, Chih Yang Kao, Guan Shyan Lin, Kai Ling Chiu, Chuan-Shian Fu, Cheng-tzung Tsai, Chia Wen Liang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2010
• Subjects: CMOS integrated circuits; CMOS technology; Logic gates; MOS devices; MOSFET circuits; Performance evaluation; Random access memory
• ISBN: 142446658X; 9781424466580
• ISSN: 1930-8876
• DOI: 10.1109/ESSDERC.2010.5618437

A simple approach for manufacturing quasi-planar tri-gate bulk MOSFET structures is demonstrated and shown to be effective for reducing variation in 6T-SRAM read and write margins, in an early 28nm CMOS technology. With optimization of the pocket implant doses, quasi-planar bulk CMOS technology can facilitate voltage scaling. It also provides a means to achieve high yield with a notch-less 6T-SRAM cell layout, to facilitate area scaling.