Thermal Modeling and Management Challenges in Heterogenous Integration: 2.5D Chiplet Platforms and Beyond

• Published in: 2024 IEEE 42nd VLSI Test Symposium (VTS) pp. 1 - 4
• Main Authors: Park, Jaehyun, Kanani, Alish, Pfromm, Lukas, Sharma, Harsh, Solanki, Parth, Tervo, Eric, Doppa, Janardhan Rao, Pande, Partha Pratim, Ogras, Umit Y.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 22-04-2024
• Subjects: 2.5D chiplet architectures; Computational modeling; Costs; Integrated circuits; large-scale integration; Memory management; Multichip modules; Reviews; Runtime; thermal modeling; Three-dimensional displays
• ISSN: 2375-1053
• DOI: 10.1109/VTS60656.2024.10538578

Heterogeneous integration using 2.5D chiplet platforms provides a new avenue for compact scale-out implementations of emerging applications, such as deep learning (DL). Integrating multiple small chiplets using a Network-on-Interposer (NoI) offers not only significant cost reductions and higher manufacturing yield compared to 2D ICs but also better thermal efficiency than 3D ICs and easier heterogeneous integration. However, dense integration and substantial compute density exacerbate thermal design problems, threatening to undermine the potential performance and cost benefits. Due to the significant role of temperature in the operation and reliability of integrated systems, it is critical to understand the role of heat in this emerging design area. However, little work has considered the thermal consequences of closely packaging a large number of computational elements. This paper overviews the thermal modeling challenges for chiplet-based 2.5D platforms, overviews existing approaches, and discusses the opportunities enabled by fast and accurate thermal models.