Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

We propose a novel cross-level verification approach for processor verification at the Register-Transfer Level (RTL). The foundation is a randomized coverage-guided instruction stream generator that produces one endless and unrestricted instruction stream that evolves dynamically at runtime. We leve...

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Bibliographic Details
Published in:2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) pp. 1123 - 1126
Main Authors: Bruns, Niklas, Herdt, Vladimir, Jentzsch, Eyck, Drechsler, Rolf
Format: Conference Proceeding
Language:English
Published: EDAA 14-03-2022
Subjects:
Aging
Computer bugs
Generators
Instruction sets
Runtime
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Summary:We propose a novel cross-level verification approach for processor verification at the Register-Transfer Level (RTL). The foundation is a randomized coverage-guided instruction stream generator that produces one endless and unrestricted instruction stream that evolves dynamically at runtime. We lever-age an Instruction Set Simulator (ISS) as a reference model in a tight co-simulation setting. Coverage information is continuously updated based on the execution state of the ISS and we employ Coverage-guided Aging to smooth out the coverage distribution of the randomized instruction stream over the time. In combination, this enables a broad and deep coverage to find intricate corner-case bugs in the RTL processor. Our case study with an industrial pipelined 32 bit RISC- V processor demonstrate the effectiveness of our approach.
ISSN:1558-1101
DOI:10.23919/DATE54114.2022.9774771