On the functional test of the cache coherency logic in multi-core systems

• Published in: 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS) pp. 1 - 4
• Main Authors: Perez Acle, J., Cantoro, R., Sanchez, E., Sonza Reorda, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-02-2015
• Subjects: Built-in self-test; Circuit faults; Coherence; Hardware; Multicore processing; Protocols
• DOI: 10.1109/LASCAS.2015.7250453

Multi-core systems are becoming particularly common, due to the high performance they can deliver. Their performance strongly depends on the availability of effective cache controllers, able to guarantee (among others) the coherence of the caches of the different cores. This paper proposes a method for the test of the cache coherence logic existing within each core in a multi-core system, resorting to a functional approach; this means that the method is based on the generation of a suitable test program, to be run in a coordinated manner on the cores composing the system. The method is able to detect hardware defects affecting this logic. The method was validated on a LEON3 multicore system.