FPGA implementation of the synchronization for IEEE 802.11n WLAN systems

• Published in: 2014 IEEE Fifth International Conference on Communications and Electronics (ICCE) pp. 280 - 284
• Main Authors: Minh-Duc Nguyen, Viet-Tan Nguyen, Tien-Dat Nguyen, Xuan-Nghia Nguyen, Vu-Thang Nguyen, Vu-Duc Ngo
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-07-2014
• Subjects: Field programmable gate arrays; FPGA; IEEE 802.11n; OFDM; Wireless LAN; Wireless LAN systems
• ISBN: 9781479950492; 1479950491
• DOI: 10.1109/CCE.2014.6916715

Normally, a premable is used for the time synchronization for IEEE 802.11n Wireless LAN (WLAN) systems. However, the synchronization is often affected by the timing of the packet detection and automatic gain control completion (AGC). Therefore, it is invalid to assume that symbol timing synchronization starts at the beginning of the preambles in conventional methods. Moreover, most current timing synchronization methods estimate a coarse time-offset of legacy short training symbols (L-STSs) using complex mathematical expressions such as the cross-correlation or auto-correlation. Implementations of these methods, therefore, are complicated and require a lot of hardware. In order to solve the above problems, an effective symbol timing synchronization method is proposed. The new method can detect the start of frame correctly and can save hardware upto 90.5%, 70.6% and 72.4% compare to conventional and previously proposed methods.