A novel energy-efficient self-correcting methodology employing INWE

• Published in: 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) pp. 1 - 4
• Main Authors: Kumar, Chaudhry Indra, Sharma, Arvind, Miryala, Sandeep, Bulusu, Anand
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-06-2016
• Subjects: Delays; Energy Efficient flip flop; error resilient circuits; Integrated circuit modeling; Inverters; INWE; Latches; Logic gates; Sub-Threshold circuits; Threshold voltage; timing errors
• DOI: 10.1109/SMACD.2016.7520744

Operating VLSI circuits at near/sub-threshold region is emerging as the most important technique for low power applications. However, due to the increasing variability in sub-threshold regime, system performance and yield is at stake. Therefore, improved circuit techniques are needed with low power overhead which can essentially improve the yield. This paper presents a timing error Self Correcting Flip-Flop (SCFF) operating at near threshold voltage. The proposed SCFF automatically corrects timing faults in sequential elements and datapaths, thereby reducing performance degradation due to variations and improves yield. The proposed technique uses Inverse Narrow Width effect (INWE) for performance optimization. The proposed methodology is evaluated by considering few custom circuits along the data-path. The simulation results show that the proposed SCFF design achieves better yield ratio for a given frequency specification, ~0.33 at 0.4v and ~0.32 at 0.35v supply voltage against existing error detection and correction methods.