AMD'S "LLANO" Fusion APU

Presents a collection of slides covering the following topics: APU architecture and floorplan; CPU core feature; graphics feature; unified video decoder feature; power gating; and turbo core.

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Bibliographic Details
Published in:	2011 IEEE Hot Chips 23 Symposium (HCS) pp. 1 - 38
Main Authors:	Foley, Denis, Steinman, Maurice, Branover, Alex, Smaus, Greg, Asaro, Antonio, Punyamurtula, Swamy, Bajic, Ljubisa
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-08-2011
Subjects:	Computer architecture Decoding Graphics processing units Ports (Computers) Video decoders
Online Access:	Get full text
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Description
Summary:	Presents a collection of slides covering the following topics: APU architecture and floorplan; CPU core feature; graphics feature; unified video decoder feature; power gating; and turbo core.
DOI:	10.1109/HOTCHIPS.2011.7477511