Fast and area efficient implementation for chaotic image encryption algorithms

• Published in: 2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS) pp. 1 - 4
• Main Authors: Ansarmohammadi, Sied Ali, Shahinfar, Saeed, Nejatollahi, Hamid
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-10-2015
• Subjects: Chaos; Chaotic Image Encryption; Encryption; FPGA; Hardware; Hardware/Software Co-Design; Image Encryption Hardware Accelerator; Runtime; Software; Software algorithms
• DOI: 10.1109/CADS.2015.7377788

The chaotic image encryption algorithm has been the focus of attention for years due to its remarkable functions in the realm of image processing. The National Digital System Design Contest of Iran 2015 was aimed to develop a fast and area efficient implementation of the chaotic image encryption algorithm. We first explored different implementations, i.e. pure software and hardware/software co-design, to find the best one to solve the contest's problem. Based on the results, we select an optimized hardware/software co-design implementation, in which a series of techniques and optimization methods are employed to improve run time of the image encryption algorithm while preserving area overhead under a sensible ceil. Our method surpasses other teams in both criteria including runtime and hardware cost adjusted runtime.