Soft error tolerance using Horizontal-Vertical-Double-Bit Diagonal parity method

• Published in: 2015 International Conference on Electrical Engineering and Information Communication Technology (ICEEICT) pp. 1 - 6
• Main Authors: Rahman, Md Shamimur, Sadi, Muhammad Sheikh, Ahammed, Sakib, Jurjens, Jan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2015
• Subjects: Double-Bit Diagonal Parity; Horizontal Parity; Soft Error Tolerance; Vertical Parity
• DOI: 10.1109/ICEEICT.2015.7307411

The likelihood of soft errors increase with system complexity, reduction in operational voltages, exponential growth in transistors per chip, increases in clock frequencies and device shrinking. As the memory bit-cell area is condensed, single event upset that would have formerly despoiled only a single bit-cell are now proficient of upsetting multiple contiguous memory bit-cells per particle strike. While these error types are beyond the error handling capabilities of the frequently used error correction codes (ECCs) for single bit, the overhead associated with moving to more sophisticated codes for multi-bit errors is considered to be too costly. To address this issue, this paper presents a new approach to detect and correct multi-bit soft error by using Horizontal-Vertical-Double-Bit-Diagonal (HVDD) parity bits with a comparatively low overhead.