Enhanced low dimensional MOSFETs with variation of high K dielectric materials

• Published in: 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) pp. 1 - 5
• Main Authors: Singh, Abhay Pratap, Baghel, R K, Tirkey, Sukeshni
• Format: Conference Proceeding
• Language: English
• Published: IEEE 18-02-2023
• Subjects: Drain induced barrier lowering (DBIL); Ions; Logic gates; MOSFET; OFF Current (IOFF); ON Current (ION); Performance evaluation; Short Channel effects (SECs); Silicon nitride; Simulation; Subthreshold slope (SS); Switches
• ISSN: 2688-0288
• DOI: 10.1109/SCEECS57921.2023.10062976

This works shows the effect of different dielectric material which are used in gate dielectric material in metal oxide semiconductor field effect transistor (MOSFET). Dielectric material like silicon dioxide (\text{SiO}_{2}) , silicon nitride (\text{Si}_{3}\mathrm{N}_{4}) , hafnium dioxide (\text{HfO}_{2}) are used in this study. Changing the gate dielectric material in MOSFETs can reduce leakage current, hence improving the device's performance metrics. For device designing and simulations computer added design tool Cogenda TCAD is used. After the simulation results are verified using MOSFET reference data, the device structure is designed at 15 nm node technology. Simulation results shows the reduction of OFF current (IoFF), higher on current to off current ratio (ION/IoFF), near ideal subthreshold slope (SS), and enhanced drain induced barrier lowering (DIBL). The proposed circuit shows the improved IOFF of the device by 2 to 3 times, ION by 1.5 times, trans-conductance (gm) by 2 times, output conductance (gd) by 1.65%, and ION/IoFF ratio by 10^{5} . Proposed device is a better replacement to present technology devices in terms of low power and high switching applications.