Nanosheet-based Device Architectures with Front/Backside Connectivity: Opportunities for S/D Engineering to Enable Advanced CMOS Logic Scaling

• Published in: 2023 21st International Workshop on Junction Technology (IWJT) pp. 1 - 5
• Main Authors: Veloso, A., Eneman, G., Matagne, P., Keersgieter, A. De, Hikavyy, A., Favia, P., Horiguchi, N.
• Format: Conference Proceeding
• Language: English
• Published: JSAP 08-06-2023
• ISSN: 2768-2153
• DOI: 10.23919/IWJT59028.2023.10175170

We report on nanosheet-based FETs as key enablers for the continuation of the CMOS logic scaling roadmap beyond finFETs. Their source/drain (S/D) definition is an important differentiator, done via inner spacers and S/D epi growth co-integration, for single or, in case of 3D stacked structures such as CFET, multiple transistor vertical levels. Different S/D-induced channel strain scenarios motivate exploration of alternative S/D epi processes and materials, particularly for NMOS stacked on top of PMOS in CFET. In parallel, for enhanced performance and higher cells scalability, power wiring can be moved to the wafer's backside (BS). In this work, taking advantage of such configuration, we will also discuss several possible options for further contact resistance (R contact ) reduction at the transistor's source, thus engineering devices from both the wafer's frontside (FS) and its BS.