Cascode GaN HEMT Gate Driving Analysis

Cascode GaN HEMT Gate Driving Analysis

The aim of this paper is to analyze the conventional cascode gate driving to understand the switching transition and to provide a design guide for the GaN HEMT and its associated packaging. A double-pulse tester has been designed and fabricated with minimum parasitic inductance to avoid unnecessary...

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Bibliographic Details
Published in:2023 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia) pp. 1 - 6
Main Authors: Heumesser, Vanessa, Lai, Jih-Sheng, Hsieh, Hsin-Che, Hsu, Johnny, Yang, Chih-Yi, Chang, Edward Y., Liu, Ching-Yao, Chieng, Wei-Hua, Hsieh, Yueh-Tsung
Format: Conference Proceeding
Language:English
Published: IEEE 27-08-2023
Subjects:
Capacitance
Cascode GaN
Gate driving
HEMT
HEMTs
Logic gates
MOSFET
SPICE
Switches
Zero voltage switching
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Summary:The aim of this paper is to analyze the conventional cascode gate driving to understand the switching transition and to provide a design guide for the GaN HEMT and its associated packaging. A double-pulse tester has been designed and fabricated with minimum parasitic inductance to avoid unnecessary parasitic ringing. The switching behaviors in both turn-on and -off are analyzed through topological study and explained through SPICE simulation. Two different cascode devices were tested to show the impact of threshold voltage and low-voltage Si MOSFET selection.
ISSN:2831-3712
DOI:10.1109/WiPDAAsia58218.2023.10261905