Design and Implementation of Pulse Compression Radar Waveforms Digital Generator and Processor with Real Time Side-lobes Suppression Optimum Filter on FPGA

Side-Lobes Suppression (SLS) in Pulse Compression (PC) radar aims to overcome the main problem of PC techniques, which is the high sidelobes level at the Matched Filter (MF) output. Thereby, enhances the overall detection performance of the radar system. Recently, a generic side-lobes suppression Op...

Full description

Bibliographic Details

Published in:	2020 12th International Conference on Electrical Engineering (ICEENG) pp. 228 - 233
Main Authors:	Metwally, Ibrahim M, Elbardawiny, Abd El Rahman H, Ahmed, Fathy M, Fahim, Hazem Z
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-07-2020
Subjects:	Field Programmable Gate Array (FPGA) Hardware Logic gates Matched Filter (MF) Matched filters Optimum Filter (OP-F) Pulse Compression (PC) Radar Real-time systems Side-Lobes Suppression (SLS) Signal generators Simulation
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!