Design of High-Performance Full Adder Using 20nm CNTFET Technology

• Published in: 2021 4th International Conference on Recent Trends in Computer Science and Technology (ICRTCST) pp. 192 - 196
• Main Authors: Naveen, G., Rao, V.R Seshagiri, N, Nirmala, L, Pavan Kalyan, Vijay, Vallabhuni, Venkateswarlu, S. China, Vallabhuni, Rajeev Ratna
• Format: Conference Proceeding
• Language: English
• Published: IEEE 11-02-2022
• Subjects: CNTFET; CNTFETs; Full adder; Low power; PDP; Semiconductor device measurement; Semiconductor device modeling; Solids; Technological innovation; Voltage; Writing
• DOI: 10.1109/ICRTCST54752.2022.9782042

Full adder was also known as basic component in any digital circuitry for microprocessors, digital signal processors and for every processing chip used in nowadays technology. The main purpose of full adder is to do basic logic along with operations of arithmetic's. Thus it allows designer for further advancement of the circuits with improvement in characteristic such as robust, compact, efficient, including scalabilities. Carbon Nanotube Field Effect Transistor (CNTFET) are came into use as substitute of CMOS innovation for planning circuits in the arising innovation. Main moto for this model is to design a advanced and high performable full adder circuit using CNTFET transistor admired by new CMOS full adder plan with cutting edge execution boundaries. To a voltage supply of 0.7V, the quantity of semiconductors was diminished to 10 and furthermore the force was generally separated in two differentiated to the top accessible adder that is based on CNTFET. This plan furnishes checked improvement when contrasted and the current plans like C-CMOS, TFA, TGA, HPSC, 18T-FA adder and so on. Similar information examination show that is 37%, 50%, and 49% improvement as far as territory, delay, and power delay contrasted and both CNTFET and CMOS based adders in existing plans. The circuit was planned in 20nm innovation and reenacted with CADENCE apparatuses.