A 2.6 e-rms Low-Random-Noise, 116.2 mW Low-Power 2-Mp Global Shutter CMOS Image Sensor with Pixel-Level ADC and In-Pixel Memory

• Published in: 2021 Symposium on VLSI Circuits pp. 1 - 2
• Main Authors: Seo, Min-Woong, Chu, Myunglae, Jung, Hyun-Yong, Kim, Suksan, Song, Jiyoun, Lee, Junan, Kim, Sung-Yong, Lee, Jongyeon, Byun, Sung-Jae, Bae, Daehee, Kim, Minkyung, Lee, Gwi-Deok, Shim, Heesung, Um, Changyong, Kim, Changhwa, Baek, In-Gyu, Kwon, Doowon, Kim, Hongki, Choi, Hyuksoon, Go, Jonghyun, Ahn, JungChak, Lee, Jaekyu, Moon, Changrok, Lee, Kyupil, Kim, Hyoung-Sub
• Format: Conference Proceeding
• Language: English
• Published: JSAP 13-06-2021
• Subjects: CMOS image sensors; Integrated circuit interconnections; Memory management; Random access memory; Stacking; Very large scale integration
• ISSN: 2158-5636
• DOI: 10.23919/VLSICircuits52068.2021.9492357

This paper presents a low-random noise of 2.6 e-rms, a low-power of 116.2 mW at video rate, and a high-speed up to 960 fps 2-mega pixels global-shutter type CMOS image sensor (CIS) using an advanced DRAM technology. To achieve a high performance global-shutter CIS, we proposed a novel architecture for the digital pixel sensor which is a remarkable global-shutter operation CIS with a pixel-wise ADC and an in-pixel digital memory. Each pixel has two small-pitch Cu-to-Cu interconnectors for the wafer-level stacking, and the pitch of each unit pixel is less than 5 μm which is the world's smallest pixel embedding both pixel-level ADC and 22-bit memories.