An efficient vector-space approach for accurately modeling fixed-point digital signal processors

• Published in: Proceedings of Digital Processing Applications (TENCON '96) Vol. 2; pp. 659 - 664 vol.2
• Main Author: Maurudis, A.S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1996
• Subjects: Digital signal processing; Fixed-point arithmetic; Floating-point arithmetic; Instruments; Libraries; Prediction algorithms; Software algorithms; Software engineering; Standards development; Vectors
• ISBN: 0780336798; 9780780336797
• DOI: 10.1109/TENCON.1996.608421

This paper presents the DSP Software Engineering (DSPSE) Fixed Arithmetic Tool (FAT/sup TM/) method for modeling DSP fixed-point processors and converting an algorithm from a floating-point model to a given DSP fixed-point processor model. All DSP fixed-point processors have associated with them a set of fixed bit length data representations for the storage and manipulation of binary information. We define a vector sub-space for each DSP fixed-point processor, as a direct sum of each distinct fixed bit length data representation sub-space. The direct sum of all DSP fixed-point processor vector subspaces forms a FAT/sup TM/ DSP vector space. Furthermore, for our discussion, we define an operator projection to be performed on our DSP vector space such that redundancy in the operational behavior of the DSPs to be modeled can be exploited. In our preferred embodiment we implement the FAT/sup TM/ vector space in a C++ environment, resulting in a Fixed Arithmetic C++ Tool (FACT/sup TM/) library for all associated fixed-point DSPs. For our own development we have created, a FACT/sup TM/ library for the Texas Instrument TMS320C54x DSP fixed-point processor. The TMS320C54x library has been used in the development of the Japanese Vector Sum Excited Linear Prediction (JVSELP) algorithm and the International Telecommunications Union G.728 standard algorithm.