A formal model of several fundamental VHDL concepts

A formal model of several fundamental VHDL concepts

This paper presents a formal model of several fundamental concepts in VHDL including the semantics of individual concurrent statements, and groups of those statements, resolution functions, delta delays, and hierarchical component structuring. Based on this model, several extensions to VHDL are prop...

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Published in:Proceedings of COMPASS'94 - 1994 IEEE 9th Annual Conference on Computer Assurance pp. 177 - 181
Main Author: Goldschlag, D.M.
Format: Conference Proceeding
Language:English
Published: IEEE 1994
Subjects:
Circuit simulation
Computational modeling
Computer languages
Delay
Discrete event simulation
Hardware design languages
Laboratories
Logic devices
Timing
US Department of Defense
Online Access:Get full text
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Abstract This paper presents a formal model of several fundamental concepts in VHDL including the semantics of individual concurrent statements, and groups of those statements, resolution functions, delta delays, and hierarchical component structuring. Based on this model, several extensions to VHDL are proposed including nondeterministic assignments and unbounded asynchrony. Nondeterminism allows the specification of environments and of classes of devices. This model naturally captures the meaning of composition of VHDL programs.< >
AbstractList This paper presents a formal model of several fundamental concepts in VHDL including the semantics of individual concurrent statements, and groups of those statements, resolution functions, delta delays, and hierarchical component structuring. Based on this model, several extensions to VHDL are proposed including nondeterministic assignments and unbounded asynchrony. Nondeterminism allows the specification of environments and of classes of devices. This model naturally captures the meaning of composition of VHDL programs.< >
Author Goldschlag, D.M.
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Snippet This paper presents a formal model of several fundamental concepts in VHDL including the semantics of individual concurrent statements, and groups of those...
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StartPage 177
SubjectTerms Circuit simulation
Computational modeling
Computer languages
Delay
Discrete event simulation
Hardware design languages
Laboratories
Logic devices
Timing
US Department of Defense
Title A formal model of several fundamental VHDL concepts
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