CMOS VT characterization by capacitance measurements in FDSOI PIN gated diodes

• Published in: 2014 44th European Solid State Device Research Conference (ESSDERC) pp. 405 - 408
• Main Authors: Navarro, Carlos, Bawedin, Maryline, Andrieu, Francois, Cluzel, Jacques, Garros, Xavier, Cristoloveanu, Sorin
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2014
• Subjects: Capacitance; Capacitance measurement; Charge carrier processes; Fully depleted; gated diode; inter-gate coupling PIN; Logic gates; MOSFET; SOI; Threshold voltage
• DOI: 10.1109/ESSDERC.2014.6948846
• ISBN: 9781479943784; 1479943789
• ISSN: 1930-8876

We present a powerful technique for the characterization of FDSOI devices. For example, in CMOS designs, the evaluation of threshold voltage for N and also P-MOSFETs is compulsory and is performed in separate devices. We propose to extract the threshold voltage for both types of transistors simultaneously by using capacitance measurements in thin fully depleted SOI PIN gated diodes. The N+ and P+ terminals guarantee the availability of both types of carrier and equilibrium conditions during all operation modes: from strong accumulation to strong inversion. Experiments together with numerical TCAD simulations are performed and discussed. It is shown that, from a single capacitance curve, it is possible to extract also the threshold voltage at the bottom interface.