Electrical model of the floating gate defect in CMOS ICs: implications on I/sub DDQ/ testing

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 13; no. 3; pp. 359 - 369
• Main Authors: Champac, V.H., Rubio, A., Figueras, J.
• Format: Journal Article
• Language: English
• Published: IEEE 01-03-1994
• Subjects: Capacitance; Circuit simulation; Circuit testing; Coupling circuits; Current supplies; MOSFETs; Power supplies; Semiconductor device modeling; SPICE; Voltage
• DOI: 10.1109/43.265677
• EISSN: 1937-4151
• ISSN: 0278-0070

The behavior of an MOS transistor with an open in the polygate path (floating transistor gate defect) is investigated and its effect on the quiescent power supply current I/sub DDQ/ is studied. The possible detection of this defect by current testing is explored in fully complementary CMOS circuits. The behavior of a transistor with its floating gate is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The poly-bulk and metal-poly capacitances are found to be two significant parameters in determining the degree of conduction on the affected transistor. The induced voltage in the floating gate and the quiescent current are estimated by analytical expressions. The model is compared with SPICE 2 simulations. Good agreement is observed between the simple analytical expressions, simulations and experimental measures performed on defective circuits. In addition, it is shown that the floating gate transistor can be modeled as a weakly conductive stuck-on transistor or as a stuck-open transistor depending on the values of the parameters characterizing the defect.< >