Disturb and its mitigation in Ferroelectric Field-Effect Transistors with Large Memory Window for NAND Flash Applications

• Published in: IEEE electron device letters p. 1
• Main Authors: Venkatesan, Prasanna, Park, Chinsung, Song, Taeyoung, Fernandes, Lance, Das, Dipjyoti, Afroze, Nashrah, Ravikumar, Priyankka Gundlapudi, Tian, Mengkun, Chen, Hang, Chern, Winston, Kim, Kijoon, Woo, Jongho, Lim, Suhwan, Kim, Kwangsoo, Kim, Wanki, Ha, Daewon, Mahapatra, Souvik, Yu, Shimeng, Datta, Suman, Khan, Asif
• Format: Journal Article
• Language: English
• Published: IEEE 24-09-2024
• Subjects: Dielectrics; Disturb; Electrons; FEFET; FeFETs; Ferroelectrics; Logic gates; NAND; Prevention and mitigation; Trap dynamics; Very large scale integration
• DOI: 10.1109/LED.2024.3467210
• EISSN: 1558-0563
• ISSN: 0741-3106

We study the disturb characteristics of ferroelectric field-effect transistors (FEFETs) with band-engineered gate stacks. We demonstrate that integrating a dielectric Al 2 O 3 layer within the ferroelectric (FE) Hf 0.5 Zr 0.5 O 2 layer in the gate stack significantly enhances the memory window (MW), achieving levels suitable for quad-level cell operation (approximately 7.5 V) while operating at a reduced write voltage (below 15 V). Despite these improvements, the band-engineered FEFET exhibits similar pass disturb characteristics in the PGM state as a standard FEFET with an FE-only gate stack. To improve the disturb characteristics, we introduce and validate a periodic refresh-based disturb mitigation scheme, analogous to strategies employed in SSD controllers and flash memory managers for traditional charge trap flash-based NAND chips. This mitigation scheme reduces disturb in the PGM state from ~28% to approximately ~4% in the band-engineered FEFETs, enabling large memory window, lowdisturb operation.