Copper Wires for High Speed Logic LSI Prepared by Low Pressure Long Throw Sputtering Method
Copper sputtering method for fabrication of high performance logic LSI was studied. Extension of target to substrate distance is effective to improve step coverage of sputtered film combined with reduced operation pressure. Step coverage of low pressure long throw sputtering method also strongly dep...
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Published in: | MATERIALS TRANSACTIONS Vol. 43; no. 7; pp. 1599 - 1604 |
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The Japan Institute of Metals and Materials
2002
Japan Science and Technology Agency |
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Abstract | Copper sputtering method for fabrication of high performance logic LSI was studied. Extension of target to substrate distance is effective to improve step coverage of sputtered film combined with reduced operation pressure. Step coverage of low pressure long throw sputtering method also strongly depends upon the feature size of trenches and holes which are formed on silicon wafer. Sub-micron holes and trenches are successfully filled with copper by using this sputtering process followed by re-flow annealing process. Hydrogen annealing process prior to the sputtering deposition on via openings is also investigated to realize good conductivity through the via. This process results in the reduction of copper oxide at the surface of copper film. Using these newly developed processes, 0.2 \\micron node BiCMOS LSI with 4 level copper interconnects was successfully fabricated and high performance of the copper interconnect system was clearly demonstrated. |
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AbstractList | Copper sputtering method for fabrication of high performance logic LSI was studied. Extension of target to substrate distance is effective to improve step coverage of sputtered film combined with reduced operation pressure. Step coverage of low pressure long throw sputtering method also strongly depends upon the feature size of trenches and holes which are formed on silicon wafer. Sub-micron holes and trenches are successfully filled with copper by using this sputtering process followed by re-flow annealing process. Hydrogen annealing process prior to the sputtering deposition on via openings is also investigated to realize good conductivity through the via. This process results in the reduction of copper oxide at the surface of copper film. Using these newly developed processes, 0.2 mu m node BiCMOS LSI with 4 level copper interconnects was successfully fabricated and high performance of the copper interconnect system was clearly demonstrated. Copper sputtering method for fabrication of high performance logic LSI was studied. Extension of target to substrate distance is effective to improve step coverage of sputtered film combined with reduced operation pressure. Step coverage of low pressure long throw sputtering method also strongly depends upon the feature size of trenches and holes which are formed on silicon wafer. Sub-micron holes and trenches are successfully filled with copper by using this sputtering process followed by re-flow annealing process. Hydrogen annealing process prior to the sputtering deposition on via openings is also investigated to realize good conductivity through the via. This process results in the reduction of copper oxide at the surface of copper film. Using these newly developed processes, 0.2 \\micron node BiCMOS LSI with 4 level copper interconnects was successfully fabricated and high performance of the copper interconnect system was clearly demonstrated. |
Author | Saito, Tatsuyuki Ohashi, Naofumi Hashimoto, Takashi Fujiwara, Tsuyoshi Yamaguchi, Hizuru |
Author_xml | – sequence: 1 fullname: Saito, Tatsuyuki organization: Device Development Center, Hitachi Ltd – sequence: 2 fullname: Hashimoto, Takashi organization: Device Development Center, Hitachi Ltd – sequence: 3 fullname: Ohashi, Naofumi organization: Device Development Center, Hitachi Ltd – sequence: 4 fullname: Fujiwara, Tsuyoshi organization: Device Development Center, Hitachi Ltd – sequence: 5 fullname: Yamaguchi, Hizuru organization: Device Development Center, Hitachi Ltd |
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Copyright | 2002 The Japan Institute of Metals and Materials Copyright Japan Science and Technology Agency 2002 |
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References | 5) T. Hashimoto, T. Kikuchi, K. Watanabe, N. Ohashi, T. Saito, H. Yamaguchi, S. Wada, N. Natsuaki, Y. Kondo, S. Kondo, Y. Homma, N. Owada and T. Ikeda: Proc. IEDM1998 (1998) pp. 209–212. 1) D. Edelstein, J. Heidenreich, R. Goldblatt, W. Cote, C. Uzoh, N. Lastig, P. Roper, T. Mcdevitt, W. Motsiff, A. Simon, J. Dukovic, R. Wachnik, H. Rathore, R. Schulz, L. Su, S. Luce and J. Slattery: Proc. IEDM1997 (1997) pp. 773–776. 3) J. Noguchi, N. Ohashi, J. Yasuda, T. Jimbo, H. Yamaguchi, N. Owada, K. Takeda and K. Hinode: Proc. 38th IRPS (2000) pp. 339–343. 4) T. Saito, N. Ohashi, J. Yasuda, J. Noguchi, T. Imai, K. Sasajima, K. Hiruma, H. Yamaguchi and N. Owada: Proc. IITC1998 (1998) pp. 160–162. 2) C.-K. Hu, R. Rosenberg, H. Rathore, D. Nguyen and B. Agarwala: Proc. IITC1999 (1999) pp. 267–269. 6) J. Onuki, M. Nihei, M. Suwa and H. Goshima: J. Vac. Sci. Technol. B17 (1999) pp. 1028–1033. 7) E. P. Barth, T. H. Ivers, P. S. McLaughlin, A. McDonald, E. N. Levine, S. E. Greco, J. Fitzsimmons, I. Melville, T. Spooner, C. De Wan, X. Chen, D. Manger, H. Nye, V. McGahay, G. A. Biery, R. D. Goldblatt and T. C. Chen: Proc. IITC2000 (2000) pp. 219–221. 1 2 3 4 5 6 7 |
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Snippet | Copper sputtering method for fabrication of high performance logic LSI was studied. Extension of target to substrate distance is effective to improve step... |
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SubjectTerms | copper hydrogen interconnect large scale integrated-circuit re-flow reduction scattering sputtering step coverage |
Title | Copper Wires for High Speed Logic LSI Prepared by Low Pressure Long Throw Sputtering Method |
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