Gate stack technology for nanoscale devices

• Published in: Materials today (Kidlington, England) Vol. 9; no. 6; pp. 32 - 40
• Main Authors: Lee, Byoung Hun, Oh, Jungwoo, Tseng, Hsing Huang, Jammy, Rajarao, Huff, Howard
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01-06-2006
• ISSN: 1369-7021; 1873-4103
• DOI: 10.1016/S1369-7021(06)71541-3

Scaling of the gate stack has been a key to enhancing the performance of complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) of past technology generations. Because the rate of gate stack scaling has diminished in recent years, the motivation for alternative gate stacks or novel device structures has increased considerably. Intense research during the last decade has led to the development of high dielectric constant (k) gate stacks that match the performance of conventional SiO2-based gate dielectrics. However, many challenges remain before alternative gate stacks can be introduced into mainstream technology. We review the current status of and challenges in gate stack research for planar CMOS devices and alternative device technologies to provide insights for future research.