Stacked SiGe nanosheets p-FET for Sub-3 nm logic applications

• Published in: Scientific reports Vol. 13; no. 1; p. 9433
• Main Authors: Chu, Chun-Lin, Hsu, Shu-Han, Chang, Wei-Yuan, Luo, Guang-Li, Chen, Szu-Hung
• Format: Journal Article
• Language: English
• Published: London Nature Publishing Group UK 09-06-2023; Nature Publishing Group; Nature Portfolio
• Subjects: 639/301; 639/925; Ammonium; Chemical vapor deposition; Etching; Fabrication; Humanities and Social Sciences; multidisciplinary; Science; Science (multidisciplinary); Semiconductor research; Transistors; Transmission electron microscopy
• ISSN: 2045-2322; 2045-2322
• DOI: 10.1038/s41598-023-36614-2

The fabrication of vertically stacked SiGe nanosheet (NS) field-effect transistors (FETs) was demonstrated in this study. The key process technologies involved in this device fabrication are low pressure chemical vapor deposition SiGe/Si multilayer epitaxy, selective etching of Si layers over SiGe layers using tetramethyl-ammonium-hydroxide wet solution, and atomic layer deposition of Y
2
O
3
gate dielectric. For the fabricated stacked SiGe NS p-GAAFETs with a gate length of 90 nm, I
ON
/I
OFF
ratio of around 5.0 × 10
5
and subthreshold swing of 75 mV/dec were confirmed via electrical measurements. Moreover, owing to its high quality of Y
2
O
3
gate dielectric, the device showed a very small drain-induced barrier-lowering phenomenon. These designs can improve the gate controllability of channel and device characteristics.