InAs/Si Hetero-Junction Nanotube Tunnel Transistors

• Published in: Scientific reports Vol. 5; no. 1; p. 9843
• Main Authors: Hanna, Amir N., Fahad, Hossain M., Hussain, Muhammad M.
• Format: Journal Article
• Language: English
• Published: London Nature Publishing Group UK 29-04-2015; Nature Publishing Group
• Subjects: 639/166/987; 639/301/1005/1007; 639/766/1130/2798; Humanities and Social Sciences; Misfit dislocations; multidisciplinary; Nanotechnology; Nanowires; Science; Silicon; Transistors
• ISSN: 2045-2322; 2045-2322
• DOI: 10.1038/srep09843

Hetero-structure tunnel junctions in non-planar gate-all-around nanowire (GAA NW) tunnel FETs (TFETs) have shown significant enhancement in ‘ON’ state tunnel current over their all-silicon counterpart. Here we show the unique concept of nanotube TFET in a hetero-structure configuration that is capable of much higher drive current as opposed to that of GAA NW TFETs.Through the use of inner/outer core-shell gates, a single III-V hetero-structured nanotube TFET leverages physically larger tunneling area while achieving higher driver current (I
ON
) and saving real estates by eliminating arraying requirement. Numerical simulations has shown that a 10 nm thin nanotube TFET with a 100 nm core gate has a 5×normalized output current compared to a 10 nm diameter GAA NW TFET.