The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series

• Published in: IEEE journal of solid-state circuits Vol. 42; no. 4; pp. 846 - 852
• Main Authors: Chang, J., Ming Huang, Shoemaker, J., Benoit, J., Szu-Liang Chen, Wei Chen, Siufu Chiu, Ganesan, R., Leong, G., Lukka, V., Rusu, S., Srivastava, D.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01-04-2007; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Arrays; Buffers; Circuit design; Circuits; Computer aided manufacturing; Computer architecture; Computers, microcomputers; Design. Technologies. Operation analysis. Testing; Dynamics; Electronics; Exact sciences and technology; Hardware; History; Infant mortality; Integrated circuits; Integrated circuits by function (including memories and processors); Leakage; Logic arrays; manufacturability; microprocessor; Microprocessors; on-die cache; power reduction; Protection; Random access memory; Redundancy; reliability; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sleep; test; Testing; Transistors; Voltage; Die; Static random access memory; Processor; Circuit design; power reduction; test; Cache memory; Random access memory; on-die cache; Transistor; Failures; Computer architecture; Integrated circuit; Microprocessor; Low-power electronics; Reliability; manufacturability
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2007.892185

The 16-way set associative, single-ported 16-MB cache for the Dual-Core Intel Xeon Processor 7100 Series uses a 0.624 mum 2 cell in a 65-nm 8-metal technology. Low power techniques are implemented in the L3 cache to minimize both leakage and dynamic power. Sleep transistors are used in the SRAM array and peripherals, reducing the cache leakage by more than 2X. Only 0.8% of the cache is powered up for a cache access. Dynamic cache line disable (Intel Cache Safe Technology) with a history buffer protects the cache from latent defects and infant mortality failures