Sn whisker evaluations in 3D microbumped structures
Sn whiskering remains a reliability concern in electronic applications. Despite extensive research on growth rates and mitigation strategies, no predictive theory is in place. Literature data are available for Cu/Sn-based films and coatings as well as for board-level and flip-chip solder bumps but d...
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Published in: | Microelectronics and reliability Vol. 54; no. 9-10; pp. 1982 - 1987 |
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Abstract | Sn whiskering remains a reliability concern in electronic applications. Despite extensive research on growth rates and mitigation strategies, no predictive theory is in place. Literature data are available for Cu/Sn-based films and coatings as well as for board-level and flip-chip solder bumps but data are scarce for scaled-down solder volumes and for higher intermetallic-to-solder ratios. The current work investigates whiskers in “isolated geometries” for 3D solder-capped Cu microbumps with >2 orders of magnitude smaller solder volumes compared to state-of-the-art. To the best of the authors’ knowledge, this is the first time Sn whisker growth is reported in isolated solder volumes (e.g. <8μm-side cube). Whiskers propensity was evaluated using JEDEC industrial specifications. The tested structures were: 5/3.5μm-thick Cu/Sn films and 15μm-diameter electroplated solder capping (Sn, SnAg, SnCu) on Cu microbumps (as-plated vs. reflowed). Selected Sn whiskers and “whisker-like” features were analysed and identified experimentally with SEM, EDX and FIB. In the absence of a predictive model, first-order and “what if” calculations based on IMC molar volume and oxide cracking hypotheses were carried out. This approach quantifies “figures of merit” for Sn whisker propensity with (1) different bump-limiting metallization (BLM) cases e.g. Cu, Ni, Co and (2) further microbump scaling. Future research recommendations are outlined to mitigate manufacturing risks by controlling “sit time” between bumping and stacking. |
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AbstractList | Sn whiskering remains a reliability concern in electronic applications. Despite extensive research on growth rates and mitigation strategies, no predictive theory is in place. Literature data are available for Cu/Sn-based films and coatings as well as for board-level and flip-chip solder bumps but data are scarce for scaled-down solder volumes and for higher intermetallic-to-solder ratios. The current work investigates whiskers in "isolated geometries" for 3D solder-capped Cu microbumps with >2 orders of magnitude smaller solder volumes compared to state-of-the-art. To the best of the authors' knowledge, this is the first time Sn whisker growth is reported in isolated solder volumes (e.g. <8 mu m-side cube). Whiskers propensity was evaluated using JEDEC industrial specifications. The tested structures were: 5/3.5 mu m-thick Cu/Sn films and 15 mu m-diameter electroplated solder capping (Sn, SnAg, SnCu) on Cu microbumps (as-plated vs. reflowed). Selected Sn whiskers and "whisker-like" features were analysed and identified experimentally with SEM, EDX and FIB. In the absence of a predictive model, first-order and "what if" calculations based on IMC molar volume and oxide cracking hypotheses were carried out. This approach quantifies "figures of merit" for Sn whisker propensity with (1) different bump-limiting metallization (BLM) cases e.g. Cu, Ni, Co and (2) further microbump scaling. Future research recommendations are outlined to mitigate manufacturing risks by controlling "sit time" between bumping and stacking. Sn whiskering remains a reliability concern in electronic applications. Despite extensive research on growth rates and mitigation strategies, no predictive theory is in place. Literature data are available for Cu/Sn-based films and coatings as well as for board-level and flip-chip solder bumps but data are scarce for scaled-down solder volumes and for higher intermetallic-to-solder ratios. The current work investigates whiskers in “isolated geometries” for 3D solder-capped Cu microbumps with >2 orders of magnitude smaller solder volumes compared to state-of-the-art. To the best of the authors’ knowledge, this is the first time Sn whisker growth is reported in isolated solder volumes (e.g. <8μm-side cube). Whiskers propensity was evaluated using JEDEC industrial specifications. The tested structures were: 5/3.5μm-thick Cu/Sn films and 15μm-diameter electroplated solder capping (Sn, SnAg, SnCu) on Cu microbumps (as-plated vs. reflowed). Selected Sn whiskers and “whisker-like” features were analysed and identified experimentally with SEM, EDX and FIB. In the absence of a predictive model, first-order and “what if” calculations based on IMC molar volume and oxide cracking hypotheses were carried out. This approach quantifies “figures of merit” for Sn whisker propensity with (1) different bump-limiting metallization (BLM) cases e.g. Cu, Ni, Co and (2) further microbump scaling. Future research recommendations are outlined to mitigate manufacturing risks by controlling “sit time” between bumping and stacking. |
Author | Willems, G. De Messemaeker, J. Wilcox, G.D. Schaubroek, D. De Wolf, I. Vakanas, G.P. Vandecasteele, B. Ashworth, M.A. |
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Cites_doi | 10.1109/TEPM.2006.890645 10.1103/PhysRevB.49.2030 10.1109/TEPM.2010.2043847 10.1557/JMR.2008.0351 10.1007/s11837-012-0442-x 10.1007/s11837-011-0178-z 10.1007/s11664-007-0284-4 10.1007/s11837-010-0105-8 10.1016/j.actamat.2010.01.027 |
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Keywords | Intermetallics Lead-free solders Microbumping 3D/TSV interconnects Whiskers State of the art Growth rate Stacking Flip-chip Cracking Metallizing Coatings Whisker Integrated circuit bonding Microelectronic fabrication Solder bump Thick film First order Electronic packaging Soldered joint Testing equipment Miniaturization Copper Reliability Static induction transistor Computer aid Figure of merit Reflow soldering |
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fullname: Tu – start-page: 283 year: 2007 ident: 10.1016/j.microrel.2014.07.110_b0015 article-title: Sn whiskers: truths and myths contributor: fullname: Osenbach – volume: 63 start-page: 62 issue: 10 year: 2011 ident: 10.1016/j.microrel.2014.07.110_b0035 article-title: Effect of layer properties on stress evolution, intermetallic volume, and density during tin whisker formation publication-title: JOM doi: 10.1007/s11837-011-0178-z contributor: fullname: Chason – volume: 18 start-page: 269 year: 2007 ident: 10.1016/j.microrel.2014.07.110_b0070 article-title: Stress analysis of spontaneous Sn whisker growth publication-title: J Mater Sci: Mater Electron contributor: fullname: Tu – volume: 36 issue: 12 year: 2007 ident: 10.1016/j.microrel.2014.07.110_b0040 article-title: Microstructure development of mechanical-deformation-induced Sn whiskers publication-title: JEM doi: 10.1007/s11664-007-0284-4 contributor: fullname: Lin – ident: 10.1016/j.microrel.2014.07.110_b0115 – start-page: 30 year: 2010 ident: 10.1016/j.microrel.2014.07.110_b0095 article-title: Real-time SEM/FIB studies of whisker growth and surface modification publication-title: JOM doi: 10.1007/s11837-010-0105-8 contributor: fullname: Jadhav – volume: 58 start-page: 3187 year: 2010 ident: 10.1016/j.microrel.2014.07.110_b0100 article-title: Reaction kinetics of Ni/Sn soldering reaction publication-title: Acta Materialia doi: 10.1016/j.actamat.2010.01.027 contributor: fullname: Görlich – ident: 10.1016/j.microrel.2014.07.110_b0075 |
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Snippet | Sn whiskering remains a reliability concern in electronic applications. Despite extensive research on growth rates and mitigation strategies, no predictive... |
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SubjectTerms | 3D/TSV interconnects Applied sciences Copper Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Intermetallics Lead-free solders Mathematical models Microbumping Microelectronic fabrication (materials and surfaces technology) Risk management Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Solders Stacking Testing, measurement, noise and reliability Three dimensional Tin Transistors Whiskers |
Title | Sn whisker evaluations in 3D microbumped structures |
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