Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under w...

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Published in:	IEEE transactions on electron devices Vol. 62; no. 9; pp. 2717 - 2723
Main Authors:	Pirro, Luca, Diab, Amer, Ionica, Irina, Ghibaudo, Gerard, Faraone, Lorenzo, Cristoloveanu, Sorin
Format:	Journal Article
Language:	English
Published:	IEEE 01-09-2015 Institute of Electrical and Electronics Engineers
Subjects:	Capacitance Capacitance measurement Engineering Sciences Frequency dependence Frequency measurement Logic gates Micro and nanotechnologies Microelectronics mobility Probes pseudo-MOSFET (Ψ-MOSFET) RC model Semiconductor device modeling Silicon silicon on insulator (SOI) split C-V Frequency dependence mobility RC model split C – V silicon on insulator (SOI) pseudo-MOSFET ( Psi -MOSFET) pseudo-MOSFET (Ψ-MOSFET) split C-V
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Abstract	Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic.
AbstractList	Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic.
Author	Ionica, Irina Faraone, Lorenzo Diab, Amer Cristoloveanu, Sorin Ghibaudo, Gerard Pirro, Luca
Author_xml	– sequence: 1 givenname: Luca surname: Pirro fullname: Pirro, Luca email: pirrol@minatec.inpg.fr organization: IMEP, Univ. Grenoble Alpes, Grenoble, France – sequence: 2 givenname: Amer surname: Diab fullname: Diab, Amer email: elhajjda@minatec.inpg.fr organization: Integrated Nanotechnol. Lab., King Abdullah Univ. of Sci. & Technol., Thuwal, Saudi Arabia – sequence: 3 givenname: Irina surname: Ionica fullname: Ionica, Irina email: Irina.Ionica@phelma.grenoble-inp.fr organization: IMEP, Univ. Grenoble Alpes, Grenoble, France – sequence: 4 givenname: Gerard surname: Ghibaudo fullname: Ghibaudo, Gerard email: ghibaudo@minatec.inpg.fr organization: IMEP, Univ. Grenoble Alpes, Grenoble, France – sequence: 5 givenname: Lorenzo surname: Faraone fullname: Faraone, Lorenzo email: lorenzo.faraone@uwa.edu.au organization: Microelectron. Res. Group, Univ. of Western Australia, Crawley, WA, Australia – sequence: 6 givenname: Sorin surname: Cristoloveanu fullname: Cristoloveanu, Sorin email: sorin@minatec.inpg.fr organization: IMEP, Univ. Grenoble Alpes, Grenoble, France
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Keywords	Frequency dependence mobility RC model split C – V silicon on insulator (SOI) pseudo-MOSFET ( Psi -MOSFET) pseudo-MOSFET (Ψ-MOSFET) split C-V
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SubjectTerms	Capacitance Capacitance measurement Engineering Sciences Frequency dependence Frequency measurement Logic gates Micro and nanotechnologies Microelectronics mobility Probes pseudo-MOSFET (Ψ-MOSFET) RC model Semiconductor device modeling Silicon silicon on insulator (SOI) split C-V
Title	Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration
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