Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

• Published in: IEEE transactions on electron devices Vol. 62; no. 9; pp. 2717 - 2723
• Main Authors: Pirro, Luca, Diab, Amer, Ionica, Irina, Ghibaudo, Gerard, Faraone, Lorenzo, Cristoloveanu, Sorin
• Format: Journal Article
• Language: English
• Published: IEEE 01-09-2015; Institute of Electrical and Electronics Engineers
• Subjects: Capacitance; Capacitance measurement; Engineering Sciences; Frequency dependence; Frequency measurement; Logic gates; Micro and nanotechnologies; Microelectronics; mobility; Probes; pseudo-MOSFET (Ψ-MOSFET); RC model; Semiconductor device modeling; Silicon; silicon on insulator (SOI); split C-V; Frequency dependence; mobility; RC model; split C – V; silicon on insulator (SOI); pseudo-MOSFET ( Psi -MOSFET); pseudo-MOSFET (Ψ-MOSFET); split C-V
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2015.2454438

Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic.