Soft-Error Rate in a Logic LSI Estimated From SET Pulse-Width Measurements

SET-induced soft-error rates (SER SET s) of logic LSIs are estimated from SET pulse-widths measured in logic cells used in logic LSIs. The estimated rates are consistent with directly measured SER SET s for logic LSIs.

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Bibliographic Details
Published in:	IEEE transactions on nuclear science Vol. 56; no. 6; pp. 3180 - 3184
Main Authors:	Makino, T., Kobayashi, D., Hirose, K., Takahashi, D., Ishii, S., Kusano, M., Onoda, S., Hirao, T., Ohshima, T.
Format:	Journal Article
Language:	English
Published:	New York IEEE 01-12-2009 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Circuit testing Clocks Estimation theory Extraterrestrial measurements Filters Frequency estimation Large scale integration Logic Logic cell Pulse measurements single event transient soft-error rate SOI Space vector pulse width modulation
Online Access:	Get full text
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Description
Summary:	SET-induced soft-error rates (SER SET s) of logic LSIs are estimated from SET pulse-widths measured in logic cells used in logic LSIs. The estimated rates are consistent with directly measured SER SET s for logic LSIs.
Bibliography:	ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23
ISSN:	0018-9499 1558-1578
DOI:	10.1109/TNS.2009.2033795