A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS

• Published in: IEEE journal of solid-state circuits Vol. 38; no. 11; pp. 1866 - 1875
• Main Authors: Hoskote, Y., Bloechel, B.A., Dermer, G.E., Erraguntla, V., Finan, D., Howard, J., Klowden, D., Narendra, S.G., Ruhl, G., Tschanz, J.W., Sriram Vangal, Veeramachaneni, V., Wilson, H., Jianping Xu, Borkar, N.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-11-2003; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerators; Central Processing Unit; Chips; CMOS; Ethernet; Ethernet networks; Hardware; High speed; Microprocessors; Open systems; Protocols; Prototypes; Search engines; TCP (protocol); TCPIP; Wire
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2003.818294

This programmable engine is designed to offload TCP inbound processing at wire speed for 10-Gb/s Ethernet, supporting 64-byte minimum packet size. This prototype chip employs a high-speed core and a specialized instruction set. It includes hardware support for dynamically reordering out-of-order packets. In a 90-nm CMOS process, the 8-mm/sup 2/ experimental chip has 460 K transistors. First silicon has been validated to be fully functional and achieves 9.64-Gb/s packet processing performance at 1.72 V and consumes 6.39 W.