Glitch-Free NAND-Based Digitally Controlled Delay-Lines

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 21; no. 1; pp. 55 - 66
• Main Author: De Caro, Davide
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-01-2013; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: All-digital delay-locked loop (ADDLL); all-digital phase-locked loop (ADPLL); Applied sciences; Circuit properties; Circuits; Circuits of signal characteristics conditioning (including delay circuits); Clock generators; Clocks; CMOS; Computer simulation; Delay; delay-line; Design. Technologies. Operation analysis. Testing; Digital circuits; digitally controlled oscillator (DCO); Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; flip-flops; Integrated circuits; Logic gates; Oscillators, resonators, synthetizers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; sense amplifier; spread-spectrum clock generator (SSCG); State of the art; Strategy; Studies; Switches; Switching circuits; Topology; Very large scale integration; Clock generator; State of the art; digitally controlled oscillator (DCO); Jitter; Driver; all-digital phase-locked loop (ADPLL); Flip-flop circuits; Spurious signal; Electronic generator; Oscillator; Complementary MOS technology; Spread spectrum; Delay time; flip-flops; Inverter; Voltage spike; delay-line; Sense amplifier; Phase locked loop; Sequential circuit; Digital control; Dimensioning; All-digital delay-locked loop (ADDLL); spread-spectrum clock generator (SSCG); Digital circuit; Delay lock loops; Delay line
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2011.2181547

The recently proposed NAND-based digitally controlled delay-lines (DCDL) present a glitching problem which may limit their employ in many applications. This paper presents a glitch-free NAND-based DCDL which overcame this limitation by opening the employ of NAND-based DCDLs in a wide range of applications. The proposed NAND-based DCDL maintains the same resolution and minimum delay of previously proposed NAND-based DCDL. The theoretical demonstration of the glitch-free operation of proposed DCDL is also derived in the paper. Following this analysis, three driving circuits for the delay control-bits are also proposed. Proposed DCDLs have been designed in a 90-nm CMOS technology and compared, in this technology, to the state-of-the-art. Simulation results show that novel circuits result in the lowest resolution, with a little worsening of the minimum delay with respect to the previously proposed DCDL with the lowest delay. Simulations also confirm the correctness of developed glitching model and sizing strategy. As example application, proposed DCDL is used to realize an All-digital spread-spectrum clock generator (SSCG). The employ of proposed DCDL in this circuit allows to reduce the peak-to-peak absolute output jitter of more than the 40% with respect to a SSCG using three-state inverter based DCDLs.