Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 57; no. 1; pp. 83 - 92
• Main Authors: Do, Anh-Tuan, Kong, Zhi-Hui, Yeo, Kiat-Seng
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-01-2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Capacitance; Circuits; CMOS; CMOS process; CMOS technology; Criteria; Devices; Electric potential; Energy consumption; Integrated circuit technology; Inverters; Latch-type sense amplifier; Mathematical models; mismatch; Process design; Random access memory; Sense amplifiers; sensing circuit; SRAM; Taylor series; Threshold voltage; Voltage
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2009.2016182

In advanced CMOS technologies where device mismatches are of major reliability concern, predicting the input-offset voltage of the sensing circuit is a crucial step in the design process as it has a direct impact on the yield. This work uses the Taylor expansion to derive a criterion to evaluate input-offset voltage of a latch-type voltage-mode sense amplifier. By innovatively setting the correct sensing criterion, this method provides a very simple, yet accurate and robust model to quantify the input-offset of the sense amplifier. The resulting offset expression incorporates three types of device mismatches, namely the threshold voltage (V th ), the trans-conductance ( K = ¿C 0x W/L) and the capacitance (C). The model is then analyzed under the worst-case scenario. It is shown that V th has the greatest influence on the offset voltage, followed by K and C mismatches. Second-order approximation is also considered when high-level mismatches are present. Extensive simulations have also been carried out to verify the accuracy of the model using three different CMOS technologies.